As semiconductor chips have become more highly integrated and the number of input/output pads per chip has increased, the need for smaller semiconductor chip packages has also increased. Accordingly, various packaging technologies have been developed to address this need. For example, the ball grid array (BGA) package provides a relatively high surface-mount density and improved electrical performance when compared with a conventional plastic package having a leadframe.
A primary difference between a ball grid array package and a conventional plastic package is that the electrical connection between the semiconductor chip and the main board is provided by a substrate including multiple layers with circuit patterns instead of a leadframe of a plastic package. In a BGA package, the semiconductor chip is attached and electrically connected to a substrate having vias which interconnect electrically conductive traces on the top layer of the substrate where the chip is attached to terminals on the bottom layer of the substrate opposite the chip. The terminals on the bottom layer of the substrate can be provided in an array pattern so that the area occupied by the BGA package on a main board is smaller than that of a conventional plastic package with peripheral terminals.
The substrate used in the BGA package, however, may still be larger than the semiconductor chip because an area without conductive traces may be required when attaching the chip to the substrate. Further reductions in the size of a BGA package may thus be limited. In response, further size reductions for semiconductor chip packages have been provided by chip-scale packages (CSP). For example, the micro-BGA (.mu.BGA) is a chip-scale package developed by Tessera and illustrated in FIG. 1. The micro-BGA is discussed in greater detail in the following reference: Crowley et al., "Chip Size Packaging Developments", TechSearch International, Inc., August 1995, pp. 101-109.
The Tessera micro-BGA package 50 includes a flexible circuit interposer 56 that interconnects chip (input/output) pads 52 and solder bumps 58. The flexible circuit interposer includes a polyimide dielectric layer 55 with vias 55a and copper traces 54. The flexible circuit interposer 56 rests on a silicon elastomer 53, and the silicon elastomer 53 is attached directly to the face of the chip 51. The traces 54 on the chip side of the interposer 56 are connected to the solder bumps 58 through the vias 55a. Ribbon leads 57 connect the traces 54 on the flexible circuit interposer 56 with the chip pads 52 on the chip 51. The leads 57 are bonded with the chip pads 52 using a technique similar to tape automated bonding (TAB). The bonding area is encapsulated with a silicone encapsulant 59. The reduced size and inductance of the micro-BGA package 50 facilitate its use for packaging high speed semiconductor chips.
The cost of manufacturing the micro-BGA package 50 may be relatively high as a result of the fabrication of the bumps 58 and the flexible circuit interposer 56. In addition, the alignment of the chip pads 52 with the leads 57 may be difficult when bonding the package. Furthermore, the tape automated bonding technique may be difficult to use with the micro-BGA package 50.